ASIC Digital Design Verification Engineer

Schaeffler is a dynamic global technology company and its success has been a result of its entrepreneurial spirit and long history of private ownership. Does that sound interesting to you? As a partner to all of the major automobile manufacturers, as well as key players in the aerospace and industrial sectors, we offer you many development opportunities. General Information This role focuses on ASIC digital design verification with emphasis on functional verification, early design verification, pre-silicon verification, functional safety verification, and post-silicon validation support. The engineer will verify legacy and new RTL designs in VHDL/Verilog using VHDL, SystemVerilog, and UVM (Universal Verification Methodology) - based testbenches, while ensuring design quality, requirement coverage, and robust silicon readiness. Your Key Responsibilities Develop and maintain verification environments for legacy/new RTL designs using VHDL, Verilog, SystemVerilog, and UVM methodologies. Prepare verification plans, test plans, testbenches, checkers, monitors, scoreboards, assertions, and reusable verification components. Perform functional, early design, and pre-silicon verification using directed, random, and constrained-random tests; debug failures through logs, waveforms, coverage, and RTL analysis. Verify functional safety requirements including error detection/correction, OV/UV/OC detection, safe-state transition, fault handling, failure notification, and diagnostics. Execute regressions, analyze functional/code/assertion coverage, drive verification closure, and document verification strategy, results, assumptions, and limitations. Support post-silicon validation by debugging digital-side issues, reproducing silicon observations in simulation, and supporting root-cause closure. Maintain verification collateral in GIT/SVN and track requirements, tasks, defects, and verification status using Polarion and Jira. Your Qualifications Bachelor’s/Master’s Degree in Electronics/Electrical Engineering, Computer Engineering, VLSI, or related field with 4 to 8 years of hands-on ASIC Digital Design and/or Design Verification experience. Experience: 4 to 8 Years Automotive IC reliability standards and tests know-how skill can be good to have. Design Knowledge Good understanding of RTL architecture, FSMs, data paths, control logics, registers, interrupts, resets, clocking, CDC/RDC basics, timing concepts, and low-power/safety-related design considerations. Ability to understand, review, and debug RTL in VHDL/Verilog and correlate design behavior with specifications, register maps, interface documents, and system requirements. Verification Expertise (Primary Focus) Strong hands-on experience in ASIC functional verification using VHDL, SystemVerilog and UVM Methodology and ability to create reusable components. Proficient in constrained-random and directed verification, stimulus generation, self-checking testbench development, assertions, functional/code/assertion coverage, coverage analysis. Experience in requirement-based verification with traceability from requirements to test cases, coverage goals, regression results, and verification evidence, especially for safety-critical digital functions. Ability to verify legacy RTL using VHDL/SystemVerilog testbenches, migrate or enhance existing environments, and support mixed-language simulation for RTL implemented in VHDL or Verilog. Good debug capability for RTL/testbench failures using waveform analysis, logs, assertions, coverage reports, reset/clock behavior, register access, interrupt/error paths, and corner-case scenarios. Tools & Technologies EDA: QuestaSim/ModelSim, Cadence Xcelium, Cadence VCS, Lint, Questa Formal, JasperGold Formal. Added advantage Questa Coverage, Questa CDC/RDC, Cadence : Incisive, SimVision, Verisium/Indago Debug. Working knowledge of Python, Perl, Tcl, Shell, Makefiles, regression automation, and CI flows. Technical Mentorship and Collaboration Strong communication, ownership, and teamwork skills with the ability to collaborate across cross-functional teams, mentor engineers, lead debug discussions, root-cause analysis, and improve verification methodology/processes. Actively participate in technical discussions, verification reviews, design reviews, debug meetings, and knowledge-sharing sessions to improve team capability by working closely with design, validation and functional safety teams across pre-silicon verification and post-silicon debug activities. Ability to mentor, support, and technically guide junior verification engineers on UVM methodology, functional verification, debug approach, coding practices, and tool usage etc., As a global company with employees around the world, it is important to us that we treat each other with respect and value all ideas and perspectives. By appreciating our differences, we inspire creativity and drive innovation. In this way, we contribute to sustainable value creation for our stakeholders and society as a whole. Together, we advance how the world moves. Exciting assignments and outstanding development opportunities await you because we impact the future with innovation. We look forward to your application. Your Contact Vitesco Technologies India Pvt. Ltd. Hemanth Hurudi