ASIC Physical Design Engineer

Job description

**Key Responsibilities** - Take full ownership of RTL-to-GDSII execution on complex designs, driving PPA and quality-of-results metrics to closure with minimal supervision. - Lead methodology and solution-focused discussions with key stakeholders across the design organization. - Work with cross-functional partners—design, CAD, and program teams—to align on implementation strategy, priorities, and schedules. - Champion and roll out new tools and techniques, driving their adoption across the engineering team. - Devise creative, non-obvious solutions to tough implementation challenges, whether through native tool capabilities or custom scripting. - Bring machine-learning-based approaches into the flow to lift productivity and improve PPA. - Trace complex issues down to precise tool or flow root causes and drive them to resolution with EDA vendor R&D teams. - Partner with globally distributed teams and mentor junior engineers as they ramp. **Tools & EDA Expertise** Hands-on fluency with the digital implementation toolchain is a core requirement—strong tool expertise keeps the learning curve short and lets you contribute to tapeouts quickly. We expect working command of the following (or their equivalents): - Cadence Genus for RTL synthesis and design-for-test insertion and Innovus for PnR. - Cadence Tempus for signoff static timing analysis (STA). - Quantus for parasitic extraction (RC/RCc). - Voltus / Voltus-Fi for power, EM, and IR-drop signoff. - Pegasus (or Siemens Calibre) for physical verification — DRC, LVS, and ERC. - Cadence Conformal for logic equivalence checking (LEC). - Scripting in Tcl, Python, or Perl for flow automation and custom utilities. - Familiarity with the equivalent Synopsys flow (Design Compiler / Fusion Compiler, IC Compiler II, PrimeTime, StarRC, Formality) is a welcome plus. **Qualifications** - BE / BTech / ME / MS / MTech in Electrical or Electronics Engineering (or a related field). **Experience & Technical Skills** - 5+ years in the digital implementation flow on advanced process nodes. - Deep expertise in one or more areas—synthesis, place-and-route, static timing analysis (STA), or EM/IR. - Strong command of scripting languages and flow development is a significant advantage. - Excellent debugging ability, with a knack for separating the critical issues from the trivial ones. **Preferred Qualifications** - Experience implementing high-speed wireline / SerDes-based blocks or SoCs. - Familiarity with low-power (UPF) methodology, DFT, and full physical signoff flows. - Hands-on with multiple tape-outs across advanced CMOS / FinFET nodes.