Role Summary
We are seeking experienced Digital Design Leads to drive RTL design and verification for next-generation semiconductor products. This role leads the digital design effort across high-speed interface and memory subsystem IPs, partnering with architecture, verification, and physical design teams to deliver silicon-ready designs.
Key Responsibilities
- Lead RTL design and micro-architecture definition for digital IP blocks from concept through tape-out.
- Own design of Ethernet and/or PCIe controller/PHY digital logic, ensuring compliance with relevant industry specifications.
- Design and integrate memory sub-system IP, including DDR, HBM, and/or LPDDR controllers and PHYs.
- Implement and optimize Forward Error Correction (FEC) logic for high-speed serial links.
- Drive design reviews, timing closure, and low-power design practices in collaboration with cross-functional teams.
- Mentor junior design engineers and coordinate with verification, DFT, and physical design teams to meet project schedules.
Required Skills & Experience
- Proven track record as an RTL Design Lead on complex digital ASIC/SoC projects.
- Hands-on experience with Ethernet and/or PCIe protocol design (controller and/or PHY level).
- Experience with Memory Sub-systems: DDR, HBM, and/or LPDDR controller/PHY design and integration.
- Working knowledge of Forward Error Correction (FEC) schemes as applied to high-speed SerDes links.
- Strong RTL coding skills (Verilog/SystemVerilog) and familiarity with standard ASIC design flows.
- Experience with timing closure, low-power design, and design-for-test (DFT) considerations.
- Strong communication skills and experience leading or mentoring design teams.
Qualifications
- Bachelor's or Master's degree (BS/MS) in Electrical Engineering, Computer Engineering, or a related field.
- Relevant years of hands-on RTL design experience in the semiconductor industry (leadership experience preferred).
California Pay Range
$180,000—$200,000 USD
