Digital - Principal Systems/DSP Engineer

Job description

Join the leading chiplet startup! As the *Principal Systems/DSP Engineer* at Eliyan, you will define and drive the DSP architecture for next-generation 224G and 448G SerDes designs powering tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will own the end-to-end system modeling, equalization algorithm development, and CDR architecture for industry-leading SerDes IPs implemented on advanced 3nm/2nm process nodes. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits ### Key Responsibilities: - Define and architect low-power DSP architectures for 224G PAM4 and 448G SerDes designs, driving key trade-offs between power, performance, and area - Develop and maintain behavioral models of mixed-signal transceiver circuits using MATLAB, Simulink, C, and/or Python for system-level performance prediction and design specification - Develop, evaluate, and optimize equalization algorithms including FFE, DFE, CTLE, and MLSE/MLSD for 224G/448G channel loss and impairment compensation - Derive and specify analog front-end (AFE), DAC/ADC, and PLL performance targets from system-level BER and link budget analyses - Design and optimize adaptive DSP algorithms for channel compensation, including adaptation convergence strategies, calibration sequencing, and robustness across PVT corners - Architect and evaluate clock and data recovery (CDR) algorithms and loop dynamics, including jitter tolerance analysis, bang-bang and linear CDR trade-offs, and frequency acquisition strategies - Perform system-level simulations and trade-off analyses balancing power consumption (digital and analog), performance, and BER requirements - Collaborate closely with analog, digital RTL, and physical design teams to ensure algorithm-to-implementation fidelity and power-efficient silicon realization - Develop and evaluate FEC solutions including inner/outer FEC architectures, RS-FEC (KP4/KP8) integration, and concatenated coding schemes per IEEE [802.3dj](http://802.3dj) and OIF CEI-224G standards - Drive silicon bring-up and characterization test plans, correlating pre-silicon system models with post-silicon measurements to validate DSP performance - Define lab validation methodologies and work with characterization teams on silicon debug, performance benchmarking, and standard compliance testing - Provide technical leadership to customers and partners on system-level link performance, interoperability, and algorithmic optimization ### Qualification: - Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields - 10+ years of experience in DSP system architecture and algorithm development for high-speed serial communication systems, with hands-on work at 112G PAM4 or higher data rates - Deep expertise in digital communication and signal processing theory, including PAM4 modulation, equalization architectures, CDR loop dynamics, and statistical channel modeling - Expert-level proficiency in system modeling using MATLAB, Simulink, C, and/or Python with demonstrated ability to build production-quality behavioral models - Strong working knowledge of high-speed serial protocols and standards including Ethernet (IEEE [802.3ck/df/dj)](http://802.3ck/df/dj)), PCIe, UCIe, and OIF CEI specifications - Solid understanding of mixed-signal circuit design concepts (DAC/ADC architectures, PLL phase noise, AFE linearity) and their impact on DSP algorithm performance and link budget - Proven ability to collaborate across analog, digital, and verification teams to translate algorithmic intent into silicon-ready implementations - Hands-on experience with 112G/224G SerDes products with proven tapeout or silicon characterization results - Detailed knowledge of OIF CEI-224G and IEEE [802.3dj](http://802.3dj) standards including link budget allocation, compliance test methodologies, and FEC performance metrics - Experience with chiplet D2D interconnects, optical/electrical interfaces (VCSEL, EML), or DRAM/HBM PHY systems a plus