DV - Staff Verification Engineer - Serdes

Job description

Join the leading chiplet startup! As an Eliyan *Staff Design Engineer*, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs. You will own verification of TX/RX equalization and CDR. This is a hands-on technical leadership role. You'll define PHY verification architecture, write UVM/SV testbenches, and make sure that designs are bug free. You will work with a cross-functional team of experts. We offer a fun work environment with excellent benefits. ONSITE M-F. ### Key Responsibilities: - Develop and execute verification plans for Serdes, other PHYs, DSP blocks, TX/RX equalization and CDR. - Create and maintain SystemVerilog/UVM-based verification environments - Write and debug SystemVerilog/UVM compliant test cases for block and chip level - Maintain regression environments - Collaborate with design team to ensure design quality - Develop, maintain, and track various test plan items and progress towards RTL freeze - Stay up to date with industry trends, emerging technologies and progress in standards’ bodies - Integration of 3rd party VIPs and coordinate feature/bug tracking requests - As a technical leader, mentor junior verification engineers - GLS simulation for functional verification and power calculations ### Required Qualifications: - BS + 7 years of verification experience with 4+ years in PHY or high-speed interfaces - Deep verification expertise in SerDes/PCIePHY, TX/RX equalization, CDR - Strong expertise in UVM/SystemVerilog, test environment and assertion coding - Experience in verifying mixed signal IPs as well as integration of VIPs ### Preferred Qualifications: - 10+ years with demonstrated verification technical leadership - Experience with Formal verification with Jasper Gold or vc-formal - Experience with GLS simulations - Python/Perl/Tcl scripting for design verification - Proficiency in 3rd party tools for regression management and coverage analysis