Failure Analysis Hardware Validation Engineer

Job description

The Product Diagnostic & Quality Center (PDQC) is seeking an experienced Hardware Validation Engineer to support the validation of electrical test hardware for NXP product analysis. The ideal candidate will have a strong Test Engineering background and experience. This role involves verifying board design quality using translated test patterns, troubleshooting hardware issues, debugging test pattern or test flows, and documenting validation results through detailed reports. The engineer will collaborate closely with the Failure Analysis Enablement (FAE), Hardware Design, Test Engineering, and Failure Analysis teams to ensure successful validation and release of test hardware. Key Responsibilities: Validate electrical test hardware to ensure accuracy and reliability for product analysis Ensure test patterns and board designs meet validation standards Troubleshoot and resolve hardware and setup issues to optimize performance Ensure workable test patterns and board designs through a thorough validation process Document validation results and findings in comprehensive reports Collaborate with cross-functional teams across multiple NXP locations to drive hardware validation and release Qualifications & Skills: Solid background in test engineering, including hardware validation methodologies Proficiency in debugging test patterns, understanding test flows and ATE testing Expertise in troubleshooting test hardware, including tester supply resources, load boards, and socket boards for Failure Analysis. Ability to collaborate effectively in a team-oriented environment and collaborate across multiple disciplines Excellent communication and report-writing skills Specific Experience: Candidates should have knowledge and hands-on experience in the following areas: Digital semiconductor testers and auxiliaries: Advantest Exascale (SMT8) Cohu Diamond 10 (ITE) Auxiliaries: oscilloscopes, high-voltage supplies Digital testing: test method development (C++/Java) and tester characterization Hardware & layout viewing tools: Allegro PCB Editor Viewer, TinyCAD Circuit Analysis: Ability to read schematics and interpret board layouts, socket profiles, and package drawings Programming: Familiarity with scripting languages such as Python, C++, Java, NI LabVIEW, Linux Shell scripting Communication Protocols: JTAG, SPI, I2C Operating Systems: Windows, Linux Industry Experience: Practical experience in a high-tech environment, particularly in New Product Introduction (NPI) Basic Concepts: Familiarity with the following concepts is an advantage: Test Program Execution: Running test mode entry and digital test patterns, data logging, and shmoo plotting Scan Testing: Automatic Test Pattern Generation (ATPG), scan testing, and scan diagnosis Memory Testing: Memory BIST (Built-In Self-Test) and bitmapping Productivity Tools: Basic knowledge of common office software (Outlook, Excel, Word) The Failure Analysis Enablement Team , part of the Product Diagnostic & Quality Center (PDQC) under NXP Global Quality, is responsible for designing, validating, and deploying test hardware solutions as well as enabling software tools such as CAD, memory bitmap, and scan diagnostic database to ensure on-time failure analysis (FA) readiness for every NXP product. The team’s work supports comprehensive product analysis from development to end-of-life, ensuring the highest quality standards for NXP customers. The FA Enablement Team provides global support across PDQC locations in Austin (USA), Bangkok (Thailand), Kaohsiung (Taiwan), Kuala Lumpur (Malaysia), Nijmegen (Netherlands), and Tianjin (China). More information about NXP in Malaysia... #LI-633a