FPGA/ASIC & SDR Engineer

Job description

With our groundbreaking satellite 5G constellation, OQ Technology is a global leader in IoT communication connectivity and associated services. We are a venture capital-backed company with a successful track record of satellite launches and are the first company in the world to disrupt the telecommunications industry by merging cellular 5G with satellites. Our technology has massive implications for the Oil & Gas, Maritime, Industry 4.0, and Transport sectors, particularly in the management and tracking of assets in remote and rural areas and in extending 5G coverage through non-terrestrial networks. As our wireless technologies continue to evolve and earn multiple awards, with funding for the next phase secured and strong commercial traction demonstrated, we are now looking to onboard a talented FPGA/ASIC & SDR Engineer to join our engineering team in Luxembourg and contribute to the continued growth and success of our organization. The role sits within the payload team and carries responsibility for the hands-on design, implementation, integration, and verification of FPGA firmware, SDR-based systems, and ASIC-level design contributions for satellite radio applications. The engineer will contribute across the development lifecycle, from RTL implementation and simulation through hardware bring-up, laboratory testing, and formal validation, with active participation in design and requirements activities under senior technical direction. Tasks The engineer will be responsible for the implementation and verification of FPGA firmware and SDR-based systems for digital transceivers, baseband processing, and digital RF functions in satellite payload and user terminal applications, with contribution to ASIC design activities where required. The following summarises the typical tasks required for the post: Design and implement FPGA firmware in VHDL and/or Verilog/SystemVerilog for PHY, baseband, and digital RF processing functions, including modulation, demodulation, FEC encoding and decoding, synchronisation, and data path logic. Implement telecommunication algorithms in FPGA from specifications supplied in MATLAB, C/C++, or equivalent reference models, and verify bit-accurate correspondence between reference and hardware outputs. Apply synthesis, place-and-route, and timing constraints to meet performance targets on Xilinx/AMD Zynq, Zynq UltraScale+, Kintex, Virtex, and Artix device families using Vivado and Vitis toolchains. Develop and execute simulation testbenches for functional and regression verification of RTL designs prior to hardware integration. Support and lead FPGA bring-up activities on target hardware platforms, including PL/PS integration over AXI interconnect, peripheral commissioning, and embedded Linux or bare-metal software integration. Perform hardware debug using JTAG-based logic analysers, integrated logic analysers (ILA), oscilloscopes, spectrum analysers, and network analysers. Execute test and validation procedures for functional, performance, and regression testing in laboratory and field environments, and record results against defined acceptance criteria. Prototype solutions rapidly using SDR platforms including Xilinx RFSOC, USRP, Analog Devices ADALM-PLUTO, AD9361/AD9371/AD9375-based platforms, and equivalent hardware to support proof-of-concept experiments and early demonstrations. Contribute to ASIC design activities including RTL development for tape-out, pre-silicon verification, and post-silicon bring-up and characterisation where applicable to mission development programmes. Evaluate and integrate Analog Devices mixed-signal RF ICs (AD936x, AD937x, ADRV900x series) with FPGA-based baseband processing, including register-level configuration, timing interface design, and RF performance characterisation. Contribute to requirements identification and design review activities, providing input on firmware implementability, interface definitions, and testability. Review applicable wireless and satellite telecommunications standards including DVB-S2/S2X, DVB-RCS2, CCSDS, and NTN waveforms, and apply relevant requirements to firmware implementation. Interface with RF hardware engineers to resolve firmware-hardware integration issues and ensure consistency of signal interfaces and system control architecture. Interface with space segment and payload system engineers to receive technical inputs and report on firmware implementation and test status. Contribute to the maintenance and improvement of the internal test laboratory capability. Contribute to technical documentation, project reviews, and technical proposals and bid responses. Work within a multidisciplinary team spanning software development, firmware development, hardware development, data analysis, and RF design. Report regularly on task progress to the responsible senior engineer or project manager. Requirements Mandatory Knowledge Bachelor’s degree in Electronic Engineering, Electrical Engineering, Telecommunications Engineering, Computer Engineering, or a closely related discipline from a recognised institution. Minimum four years of demonstrable hands-on experience in FPGA firmware development, including RTL design, simulation, synthesis, and hardware bring-up. Proficiency in VHDL and/or Verilog/SystemVerilog for RTL design and functional simulation. Demonstrated experience with Xilinx/AMD FPGA device families and Vivado or Vitis toolchains, including constraint-driven implementation and timing closure. Experience implementing digital signal processing functions in FPGA, including fixed-point arithmetic, FIR/IIR filters, FFT, FEC algorithms, and modulation/demodulation blocks. Experience with SDR platform development, including integration of baseband firmware with RF front-end hardware on platforms such as Xilinx RFSOC, Zynq SoC, USRP, or Analog Devices ADRV9002/ADRV9009/AD9361-based systems. Working knowledge of PL/PS integration using AXI4 interconnect and DMA. Experience developing testbenches and executing structured simulation and verification campaigns. Ability to implement and verify algorithms from MATLAB or C/C++ reference models. Experience performing laboratory test and validation of FPGA-based systems using standard RF and digital test equipment. Proficiency in spoken and written English. Resident in Europe with valid right to work. Desirable Knowledge Experience with satellite telecommunications applications, including familiarity with CCSDS, DVB-S2/S2X, DVB-RCS2, or equivalent waveform standards. Experience with Analog Devices RF transceiver ICs including the AD936x, AD937x, or ADRV900x series, including use of IIO framework, libiio, and associated reference designs. Exposure to ASIC design flow, including RTL for tape-out, synthesis to standard cell libraries, static timing analysis, and DFT insertion. Experience with pre-silicon verification or post-silicon validation is an advantage. Experience with Intel/Altera FPGA device families and Quartus Prime toolchain. Experience with embedded Linux integration on Zynq or Zynq UltraScale+ platforms, including Yocto build environment and kernel driver development. Familiarity with high-level synthesis tools such as Vivado HLS or Vitis HLS. Experience with GNU Radio or equivalent SDR framework for rapid prototyping. Experience with CCSDS protocol implementation including TM/TC framing, proximity link, or deep space waveforms. Familiarity with radiation-tolerant or space-grade FPGA devices and associated design constraints. Experience contributing to technical proposals or ESA project documentation. Demonstrated ability to work autonomously and manage task-level schedule commitments in a fast-paced engineering environment. Excellent interpersonal and communication skills with the ability to engage effectively with multidisciplinary engineering teams. Software & Hardware Skills VHDL, Verilog/SystemVerilog, MATLAB, C/C++, Python. Xilinx/AMD Vivado, Vitis, ISE; Intel/Altera Quartus Prime. Xilinx Zynq, Zynq UltraScale+, Kintex, Virtex, Artix device families. SDR platforms: Xilinx RFSOC, Xilinx ZCU111/ZCU216, NI USRP, Analog Devices ADALM-PLUTO, ADRV9002/ADRV9009 evaluation platforms, GNU Radio. Analog Devices RF ICs: AD9361, AD9371, AD9375, ADRV9002, ADRV9008, ADRV9009; libiio and IIO framework integration. ASIC design tools: Synopsys Design Compiler, Cadence Genus, or equivalent synthesis tools; experience with standard cell libraries and STA is an advantage. AXI4, DMA, UART, SPI, I2C, PCIe, Aurora high-speed serial interfaces. ModelSim, QuestaSim, or equivalent HDL simulation tools. RF test equipment: oscilloscope, spectrum analyser, network analyser, logic analyser. Git or equivalent version control. Linux (administration and development environment). Benefits Enjoy a 50% income tax exemption on your salary - an exceptional incentive for top talent relocating to Luxembourg, subject to eligibility conditions. Hybrid working environment. Opportunity to work on flagship EU space mission projects. A dynamic, high-growth environment with career development opportunities. Regular company events and team activities.