FPGA Hardware Board Design Engineer

Job description

Job Details: Job Description: Seeking an experienced Hardware Board Design Engineer with 8+ years of expertise in designing and delivering complex hardware platforms. This role includes driving end-to-end development of platform hardware and translates platform-level requirements to circuit and component-level specifications. Designs, develops, modifies, and evaluates electronic parts, components, PCB, or integrated circuitry for hardware platforms, electrical engineering applications, and equipment. Conducts logical design of printed circuit boards through component definition and schematic capture, defines component placement and circuit trace routing rules, and oversees board layout from feasibility studies to board tape-out while meeting multi-disciplinary platform-level requirements. Considers BOM cost and availability data versus design trade-offs at the board and system levels. This role also responsible for driving end‑to‑end board design—from capturing platform-level requirements to supporting architects in defining system design strategies, schematic development, component selection, and platform bring‑up. The candidate should possess in depth technical knowledge in high‑speed digital, analog, and mixed-signal designs. Exposure to silicon hardware or software validation and characterization platforms will be a strong plus. Key Responsibilities Lead the end‑to‑end design and development of hardware platforms , translating based on system architecture and specifications. Expertise in complex processor-, FPGA-, and ASIC‑based systems , ensuring alignment with platform performance, power, thermal, and cost objectives. Develop and review circuit designs , simulations, and trade‑off analyses to ensure robust and scalable hardware solutions. Review PCB design rules , including component placement, high‑speed routing constraints, stack‑up definitions, and signal/power integrity considerations. Review design simulations (SI/PI/Thermal) results. Responsible to drive the schematic capture, PCB layout , and design package creation from feasibility through tape‑out. Evaluate and optimize BOM cost, part availability , and risk mitigation strategies for the platform. Lead board bring-up, power-on, and platform debug activities in collaboration with architects, validation engineers, and system integration teams. Resolve complex system-level issues across electrical, firmware, mechanical, thermal, and manufacturing domains. Work closely with cross-functional teams including architecture, verification, validation, firmware, manufacturing, and customer engineering . Integrate feedback to continuously refine design methodologies and enhance platform robustness. Qualifications: Bachelor’s or Master’s degree in Electronics & Communication, Electrical Engineering , or related field. 8+ years of experience in hardware board design life-cycle. Strong expertise in processor, FPGA, and SoC-based system design . Proficiency in circuit design, analysis, and simulation . Hands-on experience with key EDA tools such as Concept HDL, OrCAD, Allegro or equivalent. Expertise in high‑speed digital, analog, and mixed-signal design principles. Experience in embedded, telecom, or RF-based hardware platforms is a plus. Exposure to thermal and mechanical design review and integration is an added advantage. (Advantageous) Experience in silicon validation, electrical characterization, test card design , or platform enablement for early silicon bring-up. Job Type: Regular Shift: Shift 1 (Malaysia) Primary Location: Penang 15, Penang, Malaysia Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.