Internship - FPGA Hardware Design - PQ Cryptography Hardware Accelerator

Job description

# Internship - FPGA Hardware Design - PQ Cryptography Hardware Accelerator > Cryptonext Security · Paris, France · Temporary · Posted 2026-08-23 **Workplace:** on_site ## Description ### Who we are CryptoNext Security is a deeptech startup specializing in post-quantum cryptography. Our solutions help businesses and institutions prepare for a future where quantum computers will challenge traditional data security. We work with leading clients in finance, defense, and telecommunications. ### **About the role** As part of an exploratory project on **hardware accelerators for post-quantum cryptography (PQC)**, we are looking for a highly motivated **FPGA Hardware Design Engineer** to take ownership of a key strategic project at the intersection of **hardware/software codesign (FPGA development and low-level C)** and **post-quantum cryptographic accelerators**. You will work on the design, integration, and evaluation of hardware accelerators for well-identified mathematical functions used in post-quantum cryptographic algorithms, with a strong focus on demonstrating concrete performance benefits on a real embedded platform. **Your mission** You will study state-of-the-art approaches described in the scientific literature on PQC hardware acceleration, including relevant academic work such as [this recent study](https://dl.acm.org/doi/epdf/10.1145/3689939.3695785), and implement the selected ones. You will focus in particular on the **Number Theoretic Transform (NTT)** and the **Keccak state permutation function**, two key computational functions involved in the implementation of algorithms such as ML-KEM and ML-DSA (lattice-based PQC algorithms). You will be responsible for **developing system-level RTL code using SystemVerilog**, integrating the resulting accelerators into a complete hardware/software system, and evaluating their impact on application-level performance. The target platform will be an **AMD Xilinx ZCU104 development board**, equipped with a **Zynq UltraScale+ MPSoC**. The primary objective of the internship is to demonstrate, on the target platform, that a hardware accelerator for either the **NTT** or the **Keccak permutation** can effectively accelerate the corresponding **ML-KEM** or **ML-DSA** implementation in the **CryptoNext Quantum Safe Library (C-QSL)**. ## Requirements **Required skills** ### Must-have - **FPGA development, RTL design using Verilog, SystemVerilog or VHDL** - Experience with **AMD Vivado** or **Intel Altera Quartus** and FPGA development platforms - Good programming skills in **C** under **Linux**, with basic knowledge of assembly language - Strong interest in hardware/software codesign and embedded systems - Experience with **Git** and standard software development workflows - Familiarity with **shell scripting**, **Makefiles**, and compiler toolchains - Experience using **profilers and debuggers** to analyze and optimize software performance - Ability to work independently, investigate technical problems, and communicate results clearly ### Nice-to-have - Knowledge of **AMBA protocols**, such as **AXI, AHB, APB, or CHI** - Experience with **JTAG-based debugging** - Experience with **QEMU**, including the **Xilinx fork of QEMU** - Experience with **QEMU/SystemC/Verilator co-simulation** - Previous exposure to **post-quantum cryptography**, lattice-based cryptography, **ML-KEM**, **ML-DSA**, NTT or DFT, or Keccak (or more generally hash functions) - Familiarity with embedded Linux and **Zynq UltraScale+ MPSoC** architectures ## Benefits **Internship details** - **Duration:** 6 months - **Period:** December 2026 – June 2027 - **Education:** Final-year engineering student or **M2 / Master's degree** in computer engineering, electrical engineering, embedded systems, microelectronics, or a related field ## Apply [Apply at Cryptonext Security](https://apply.workable.com/cryptonext-security/j/3F404B7363/apply) --- Powered by [Workable](https://www.workable.com)