Lead EDA Engineer

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at and on LinkedIn and X . ADI is seeking a Lead EDA Engineer to lead backend physical verification strategy and design enablement for analog and mixed-signal teams across multiple programs and advanced process nodes. This role serves as a technical authority for Calibre-based verification flows, foundry rule integration, signoff readiness, and the infrastructure that supports efficient execution across sites. The engineer in this role will work from concept through tapeout, shaping methodologies, resolving critical flow issues, and driving improvements that increase engineering velocity, verification quality, and resource efficiency. Key Responsibilities Technical Leadership : Serve as a recognized technical authority for backend physical verification flows, signoff methodology, and design team support across multiple projects and organizations Verification Strategy : Define, develop, and evolve Calibre-based DRC, LVS, ERC, PERC, and extraction flows that support analog and mixed-signal development at advanced nodes Critical Debug and Escalation : Lead resolution of the most complex runset, rule deck, extraction, and signoff issues, especially those with cross-project or tapeout impact Foundry and Node Enablement : Drive foundry rule file intake, validation, integration, and release readiness for new process nodes and rule deck updates Tapeout Readiness : Own or guide final signoff execution, including waiver governance, antenna-related issue closure, final verification checks, and tapeout deliverables Project and Team Enablement : Partner closely with analog layout, design, and CAD teams to identify issues early, establish robust project setups, and improve verification effectiveness before problems become schedule risks Internal Tool and Flow Innovation : Build and guide internal automation, dashboards, and verification utilities that improve debug visibility, result analysis, license efficiency, and run resource optimization Infrastructure Influence : Shape multi-site EDA infrastructure, compute farm usage, license allocation strategy, and environment reliability to support scalable execution across geographically distributed teams Documentation, Standards, and Mentorship : Establish best practices, create technical guidance, and mentor engineers through training, documentation, and day-to-day support on verification methodologies Must Have Skills Physical Verification Expertise : Deep experience leading IC backend physical verification and signoff flows, including DRC, LVS, ERC, PERC, parasitic extraction, and tapeout readiness Calibre Technical Mastery : Expert proficiency with Mentor Calibre, including development and debug of SVRF and TVF rule sets and resolution of complex verification issues Advanced Node and Foundry Experience : Strong experience supporting TSMC design rules, tapeout procedures, and foundry interfaces at advanced nodes such as 16nm, 5nm, and 4nm Flow Architecture and Debug Leadership : Proven ability to define verification methodologies, solve difficult runset and rule deck issues, and lead high-impact debug efforts across teams Scripting and Tool Development : Strong capability in Python, Tcl, Shell, or similar languages, with experience building internal tools, automation, dashboards, or supporting infrastructure EDA Infrastructure Depth : Strong understanding of Linux-based EDA environments, compute infrastructure, license utilization, and distributed engineering workflows Cross-Functional Influence : Ability to work across Design, Layout, CAD, and program teams, align priorities, and drive technical outcomes in a fast-paced multi-project environment Analog Layout and Physical Design Understanding : Strong understanding of analog IC layout practices, physical verification challenges, and signoff requirements Preferred Education and Experience BS or MS in Electrical Engineering, Computer Engineering, or a related field, or an equivalent combination of education and 10+ years of related experience Experience supporting digital physical design or place-and-route verification flows Experience with Perforce for design data management Experience with Cadence Virtuoso customization, including SKILL, bindkeys, or layout environment setup Experience with EDA license management, run resource optimization, or multi-site compute coordination Experience building GUI-based tools, reporting systems, or verification analytics dashboards Familiarity with AI-assisted methods that improve engineering productivity, debug efficiency, or flow effectiveness Experience managing foundry rule deck support across multiple process nodes and releases #LI-CC1 For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days