๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ญ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฏ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ญ๐ฑ-๐ฏ๐ฌ ๐๐ฃ๐)Experience: 3+ yrsLocation: Bengaluru, Karnataka, IndiaJob Type: Full-timeWe are looking for an experienced Physical Verification / Layout Verification Engineer to support the verification and sign-off of complex VLSI designs. The role involves ensuring physical layouts meet foundry design rules and are electrically and physically consistent with the intended design before tape-out.The ideal candidate will have strong hands-on expertise in DRC, LVS, ERC, antenna, density checks, and physical verification, with practical experience debugging complex layout issues and supporting block/IP-level sign-off.RequirementsKey ResponsibilitiesPerform physical verification and layout verification for VLSI designs at block, IP, and chip levels.Execute and analyze DRC, LVS, ERC, antenna, and density checks using industry-standard verification tools.Work extensively with Siemens Calibre or equivalent physical verification platforms.Debug and resolve complex LVS shorts, opens, device mismatches, connectivity issues, and extraction errors.Analyze DRC and other rule violations and work with layout teams to drive timely closure.Review layout connectivity and ensure consistency between schematic/netlist and physical implementation.Support block/IP-level physical sign-off and tape-out activities.Collaborate with layout, circuit design, technology, and CAD teams to resolve verification issues.Analyze extracted devices and parasitic information where required for verification and debugging.Ensure layouts comply with applicable foundry design rules and CMOS technology requirements.Develop and maintain scripts and utilities using Perl, Python, Shell, or TCL to automate repetitive verification and reporting activities.Improve physical verification workflows, methodologies, and turnaround time through automation.Track verification status, identify critical issues, and communicate progress and risks to relevant stakeholders.Support verification during multiple design iterations and ensure all sign-off requirements are completed before tape-out.Maintain clear documentation of verification results, issues, fixes, and sign-off activities.What's Makes You a Great Fit3+ years of hands-on experience in VLSI layout verification, physical verification, or related semiconductor design roles.Strong practical expertise in DRC, LVS, ERC, antenna, and density verification.Proven experience with Siemens Calibre or equivalent physical verification tools.Strong debugging skills with experience resolving LVS shorts, opens, device mismatches, connectivity issues, and rule violations.Good understanding of CMOS layout concepts, device extraction, physical connectivity, and foundry design rules.Experience supporting IP/block-level sign-off and tape-out milestones.Proficiency in at least one scripting language such as Perl, Python, Shell, or TCL.Strong analytical and problem-solving abilities with excellent attention to detail.Ability to work effectively with layout, circuit design, CAD, and technology teams.Comfortable working in a fast-paced semiconductor development environment with tight sign-off deadlines.Strong ownership of verification deliverables and ability to independently drive issues through closure.Good communication skills and the ability to clearly explain technical verification issues and their resolutions.
๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ญ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฏ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ญ๐ฑ-๐ฏ๐ฌ ๐๐ฃ๐)
Experience: 3+ yrs
Location: Bengaluru, Karnataka, India
Job Type: Full-time
We are looking for an experienced Physical Verification / Layout Verification Engineer to support the verification and sign-off of complex VLSI designs. The role involves ensuring physical layouts meet foundry design rules and are electrically and physically consistent with the intended design before tape-out.
The ideal candidate will have strong hands-on expertise in DRC, LVS, ERC, antenna, density checks, and physical verification, with practical experience debugging complex layout issues and supporting block/IP-level sign-off.
Requirements
Key Responsibilities
- Perform physical verification and layout verification for VLSI designs at block, IP, and chip levels.
- Execute and analyze DRC, LVS, ERC, antenna, and density checks using industry-standard verification tools.
- Work extensively with Siemens Calibre or equivalent physical verification platforms.
- Debug and resolve complex LVS shorts, opens, device mismatches, connectivity issues, and extraction errors.
- Analyze DRC and other rule violations and work with layout teams to drive timely closure.
- Review layout connectivity and ensure consistency between schematic/netlist and physical implementation.
- Support block/IP-level physical sign-off and tape-out activities.
- Collaborate with layout, circuit design, technology, and CAD teams to resolve verification issues.
- Analyze extracted devices and parasitic information where required for verification and debugging.
- Ensure layouts comply with applicable foundry design rules and CMOS technology requirements.
- Develop and maintain scripts and utilities using Perl, Python, Shell, or TCL to automate repetitive verification and reporting activities.
- Improve physical verification workflows, methodologies, and turnaround time through automation.
- Track verification status, identify critical issues, and communicate progress and risks to relevant stakeholders.
- Support verification during multiple design iterations and ensure all sign-off requirements are completed before tape-out.
- Maintain clear documentation of verification results, issues, fixes, and sign-off activities.
What's Makes You a Great Fit
- 3+ years of hands-on experience in VLSI layout verification, physical verification, or related semiconductor design roles.
- Strong practical expertise in DRC, LVS, ERC, antenna, and density verification.
- Proven experience with Siemens Calibre or equivalent physical verification tools.
- Strong debugging skills with experience resolving LVS shorts, opens, device mismatches, connectivity issues, and rule violations.
- Good understanding of CMOS layout concepts, device extraction, physical connectivity, and foundry design rules.
- Experience supporting IP/block-level sign-off and tape-out milestones.
- Proficiency in at least one scripting language such as Perl, Python, Shell, or TCL.
- Strong analytical and problem-solving abilities with excellent attention to detail.
- Ability to work effectively with layout, circuit design, CAD, and technology teams.
- Comfortable working in a fast-paced semiconductor development environment with tight sign-off deadlines.
- Strong ownership of verification deliverables and ability to independently drive issues through closure.
- Good communication skills and the ability to clearly explain technical verification issues and their resolutions.
At Weekday (backed by YC; also Product Hunt #1 product of the day), we are building the next frontier in hiring. We have built the largest database of white collar talent in India and have built outreach tools on top of it to generate highest response rates.
At Weekday (backed by YC; also Product Hunt #1 product of the day), we are building the next frontier in hiring. We have built the largest database of white collar talent in India and have built outreach tools on top of it to generate highest response rates.
