RTL Design Lead Engineer

Position Summary Role and Responsibilities About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Roles and Responsibilities • Technically managing design and development of Storage IPs. Prepare project plan, risk management plan, schedule tracking of state of the art, cutting edge designs, ensuring quality by sticking to company defined process. Architecture, Design and RTL development for storage controller IP's based on NVMe, UFS, and high speed peripheral bus standards such as PCIe and CXL. • Interfacing with cross-functional teams like Verification, Validation. SoC and FW . • Ensuring quality of design using Lint and CDC checks. • Synthesis, Area and power optimization. • Developing the timing constraints ( SDC) and ECO scripts. Necessary Skills / Attributes .• Project Management. Working experience in complex IP Design to meet market leading PPA metrics • Experience in designing and RTL coding using Verilog /System Verilog/VHDL. • Design QC using lint/CDC/DFT • Compile , elaboration and simulations for QC. Experience with VCS/NCsim, Verdi, and Spyglass. • Understanding of storage controller Architectures, Peripherals, Buses/Interconnects and Power Management. • Understanding of Bus Architectures (AXI/AHB), NOC (Network-on-Chip ) and ARM CPU Architectures. • Experience in writing functional design doc and/or functional specifications. • Experience in synthesis using Synopsys Design Compiler ( DC) and developing timing constraints ( SDC) and Timing analysis. • Experience in developing/understanding of ECOs • Working experience in teams with collaboration of effort between Verification, SoC integration, Physical Design and DFT Additional Qualifications (preferred) • Experience in RTL integration tools like Magillem is added advantage. • Working experience in High speed serial protocols like PCIe, NVMe, UFS Familiarity with FPGA based development is additional plus • Team player, can-do attitude is desirable. Passion for working on cutting edge technologies and ability to debug is highly desirable. Experience – 14 to 20 Years Qualifications Disclaimer Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law. Skills and Qualifications * Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here .