Senior Digital / Mixed-Signal IC Design or Verification Engineer

Job description

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Senior Digital / Mixed-Signal IC Design or Verification Engineer Location: Mendota Heights, MN or Broomfield, CO Job Description Summary Join Broadcom, a global technology leader and Fortune 500 powerhouse at the forefront of semiconductor innovation and AI infrastructure. Within our specialized Mixed-Signal ASIC division, we offer an exciting position in the explosive growth area of Data Center Enterprise Storage, where we build the critical IP responsible for providing low-power, high-performance analog and mixed-signal products. In this role, you will develop advanced semiconductor devices to support high-capacity storage needs across all top-tier service providers. You will work with highly talented teams to meet company business goals while growing your skills. We are looking for a Senior Digital IC Design or Mixed-Signal Verification Engineer to act as a methodology leader and key technical bridge for our worldwide engineering organization. This unique opportunity allows you to drive quality initiatives, pioneer modern automation (including AI-assisted workflows), and establish robust methodologies across our US and Asia design centers. Key Responsibilities Act as the primary technical liaison between local US design teams and global cross-functional teams, translating complex specifications into seamless execution. Provide technical support through all phases of product development: testing, yield analysis, characterization, reliability analysis, qualification, and release to manufacturing. Adhere to strict schedule, die size, and power commitments. Conduct detailed design reviews with internal and external customers. Digital IC Design: Define system requirements, digital control functions, and block partitions for next-generation preamplifier products. Perform digital logic design, Verilog coding, logic synthesis, formal verification, static timing analysis, and place and route. Support integrating the digital core with analog circuitry into a completed integrated circuit. Perform transistor-level high-speed digital IC design for custom cells and blocks. Digital Mixed Signal Verification: Architect, develop, and maintain advanced UVM-based testbenches for the functional verification of complex mixed-signal ASICs. Own verification efforts at both the block and system levels for major tape-out projects, driving functional and code coverage to closure. Champion verification quality by integrating new methodologies (e.g., SVA, UVM/OVM) to reduce mixed-signal validation bottlenecks. Lead initiatives to explore and integrate modern automation and AI-assisted verification workflows to accelerate testbench generation and debug efficiency. Qualifications & Skills Core Requirements (All Candidates): Education / Experience: Bachelors in Engineering and 8+ years of related experience; or Masters degree in Engineering and 6+ years of related experience Communication: Excellent spoken and written communication skills, and the proven ability to coordinate technical problem-solving across global teams. Analytical: Proven ability to apply advanced math and physics to solve complex engineering problems. Bonus: An understanding of silicon process technologies (CMOS and Bipolar) and device physics is a strong plus. Expertise across both design and verification domains is highly desired. Specialized Skills (Design Focus): Strong hands-on experience with ASIC EDA tools used in synthesis, simulation, static timing analysis, formal verification, and place & route. Deep familiarity with Verilog/VHDL RTL coding and logic design. Specialized Skills (Verification Focus): Deep expertise in coverage-driven verification processes and frameworks (UVM/OVM). Strong understanding of event-driven simulator-based modeling techniques and how digital logic interacts with analog boundaries. Hands-on experience with SystemVerilog Assertions (SVA) and behavioral modeling of analog circuits. Proficiency in scripting (Python, Perl, TCL, etc.) to automate verification workflows, manage regressions, and streamline simulation infrastructure. Why Broadcom? Beyond our highly competitive compensation and RSU packages, this role is based in our Mendota Heights, MN or Broomfield, CO design centers. These locations offer a premier quality of life, excellent schools, and a lower cost of living compared to traditional tech hubs, all while providing the career stability and massive engineering resources of a global semiconductor leader. Compensation and Benefits The annual base salary range for this position is USD 109,700.00 To USD 175,500.00 As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.