Senior Engineer (Level 2)

Job description

Position: Senior Engineer (Level 2) Job Description: Design RF and high-frequency analog circuits for high-speed SerDes PHY SoCs including LNAs, mixers, VCOs, PLL building blocks, and high-speed I/O drivers operating at multi-GHz frequencies - Develop impedance-matched RF front-ends for high-speed SerDes transmitters and receivers, minimizing signal reflections, return loss, and insertion loss across the target frequency range - Design on-chip passive structures transmission lines, baluns, transformers, and inductors using electromagnetic (EM) simulation to meet RF performance targets - Address RF signal integrity challenges crosstalk, substrate coupling, ground bounce, and power supply noise in complex mixed-signal SoC environments - Develop EMI-resilient circuit topologies for automotive Ethernet PHY front-ends that maintain performance under conducted and radiated EMI per automotive standards (CISPR 25, ISO 11452) - Perform EM/RF simulation using tools such as Cadence EMX, Keysight ADS, ANSYS HFSS, or Momentum for passive structure characterization and signal integrity analysis - Collaborate with analog and digital teams for RF-aware SoC integration managing RF-to-digital isolation, substrate noise coupling, and mixed-signal co-existence - Conduct RF characterization and measurement on silicon S-parameter measurements, noise figure, phase noise, and spurious emission characterization in lab environments Location: IN-KA-Bangalore, India (eInfochips) Time Type: Full time Job Category: Engineering Services