Senior/Engineer STPG Product Engineering - Probe

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description Summary The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM) . This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior , and driving yield, quality, and test‑cost outcomes . The focus is on interpreting design intent, device operation, and process interactions , and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements. The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle. Key Responsibilities Probe Coverage Strategy & Ownership Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands. Define, release, and sustain probe test flows from first silicon through qualification and HVM , ensuring coverage objectives are met without unnecessary test overhead. Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications , with clear alignment to downstream test. Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans. Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging. Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage. Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk . Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning). First Silicon Bring‑Up & Device Characterization Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups. Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy. Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content. Provide early silicon learning to accelerate probe flow stabilization and yield ramp . Yield, Quality & Reliability Enablement Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe. Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams. Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently. Test Efficiency & Cost Optimization Drive test efficiency improvements through coverage right‑sizing and flow optimization , aligned to product and market needs. Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts. Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding. Data, Analytics & AI Enablement Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support. Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization . Apply data‑driven insights to continuously improve probe effectiveness and efficiency. Experience Level & Entry Consideration This role is open to both early‑career and experienced engineers , with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact . Fresh Bachelor’s/Master’s / PhD Graduates Strong fundamentals in semiconductor devices, circuits, physics, or process technology . Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis . Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding . Experienced Engineers (Eligible for Higher GJS) Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles . Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs . Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑making . Required Qualifications Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field . Strong fundamentals in semiconductor devices, wafer test, and product engineering . Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions. Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration . Strong analytical skills and ability to drive structured root‑cause analysis . Effective communication skills and ability to work across global, cross‑functional teams . Preferred Qualifications Experience with NAND / memory products . Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues. Exposure to probe flow optimization, yield learning, or test cost reduction . Familiarity with DFT verification, reliability screening, or test correlation methodologies . Experience with Python, SQL, JMP, or data / ML tools . Demonstrated ability to independently drive complex technical problems from concept through execution . Career Growth & Impact Direct ownership of probe strategy and quality outcomes across the product lifecycle. Exposure to advanced technology nodes , customer‑driven requirements, and large‑scale manufacturing systems. Clear growth paths across senior technical contributor , product leadership, or people management tracks within STPG Product Engineering . About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. 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