Senior Lead Engineer – Memory design

Job description

CTO/Frontend Innovation/NVM Design Technology Department is responsible for all embedded Non-Volatile Memory deployment across NXP business and product lines. Embedded NVM encompasses nearly all technology nodes and products which integrate Logic NVM, Flash or disruptive memory solutions (e.g. RRAM, MRAM). The implementation of Embedded NVM technologies that enhance application capabilities is a competitive advantage in the marketplace. In this position, we are looking for an NVM IP Platform Lead to join our NXP’s NVM IP design group in Bangalore, India. Are you able to manage efficiently a multi-technology NVM IP portfolio, ensure the highest level of quality, and develop automated IP management solutions? Can you team up with 3rd-party NVM IP vendors and NXP product design teams, to enable the high-quality and scalable NVM IP solutions across all NXP’s vertical markets? Scope of Responsibilities/Expectations As the NVM IP Platform Lead for our newly formed Bangalore team, you will be part of a Global NVM design department. You will be leading the NVM IP onboarding, release and support competence for a wide 3rd-party NVM and NXP-proprietary IP platform including Logic-NVM, Flash, RRAM and MRAM. Your responsibilities will encompass: Support a complex 3rd-party NVM and NXP-proprietary NVM IP portfolio spanning across the whole technology spectrum of the company from 180nm to 5nm Develop an automated IP onboarding and release flow to ensure flawless and efficient execution Execute IP onboarding (IP design kit preparation and verification) and release to SoC design team Support design SoC teams with NVM IP integration and troubleshooting Interact directly with 3rd-party vendors and silicon foundries Team up with NXP NVM design team in Bangalore, EU and US Mentor junior engineers growing in the NVM field Specific skills & knowledge BS or MS in Electrical Engineering with +8 years of experience in design and/or flow automation. Hands-on experience on quality-managed Analog-Mixed signals design flows, tools and methodologies (Cadence and Synopsys) Hands-on experience in scripting and flow automation Knowledge of NVM technology, macro architecture and design is highly desired (eFuse, OTP, Flash, MRAM, RRAM) Excellent communication skills with proven experience in international relationships and available for occasional travel. Very good knowledge of quality managed design flows, tools and methodologies. More information about NXP in India... #LI-7013