Senior Silicon Design Engineer

Job description

**Overview** Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Shared and Custom IP & Silicon (SCIPS) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a **Senior Silicon Design Engineer** to work on leading edge custom IP development as part of the SCIPS (Semi-Custom and Central IP Silicon) team within CSME (Compute Silicon & Manufacturing Engineering), the team responsible for the Azure Cobalt chips. The candidate should excel at collaborating with other engineers to solve complex technical challenges. **Responsibilities** The candidate for this position will be expected and able to complete the following responsibilities: - Own development of custom IPs RTL from microarchitecture to RTL implementation, verification, and post-silicon validation. - Collaborate with architecture, SoC, firmware, verification, and physical design teams to deliver high-quality IP solutions. - Develop high-performance, power-efficient RTL designs and drive PPA optimization across the design lifecycle. - Lead design signoff activities including CDC, RDC, LINT, synthesis, STA, and timing closure. - Design leading edge hardware algorithms to provide hardware acceleration of key data processing operations. - Drive pre-silicon and post-silicon debug, silicon bring-up, and root-cause analysis of complex system issues. - Mentor engineers and champion design excellence through reviews, automation, and continuous methodology improvements. **Qualifications** **Minimum Qualifications:** - Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience - OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience - OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience - OR equivalent experience. **Other Requirements:** Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: - Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. - This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. **Preferred Qualifications:** - 3+ years experience in digital logic design in SystemVerilog/Verilog/VHDL - 3+ years experience running synthesis/static check tools including RTL synthesis, lint, CDC, RDC, and/or LEC - Proficient expertise in digital design, microarchitecture specification development, and synthesizable RTL implementation. - Ability to read and write code in Python, Perl, C/C++, C#, or related language - Experience developing and optimizing high-speed CMOS designs, including power, performance, and area tradeoff analysis. - Proficient debugging, problem-solving, and cross-functional collaboration skills throughout the IP development lifecycle. - Proficient knowledge of industry-standard interconnect protocols, including AMBA AXI. - Experience with synthesis, floorplanning, static timing analysis, timing closure, and collaboration with physical design teams. - Proficient written and verbal communication skills, with the ability to work independently and collaborate effectively across teams. #SCHIE #CSME #SCIPS Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. --- Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about [**requesting accommodations.**](https://careers.microsoft.com/v2/global/en/accessibility.html)