Senior/Staff Design Verification Engineer (SOC)

Job description

About Bitdeer: Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud. Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This includes equipment procurement, transport logistics, datacenter design and construction, equipment management, and network and facility operations. Bitdeer also offers advanced cloud capabilities to customers with a high demand for artificial intelligence. Headquartered in Singapore, Bitdeer operates globally with a diversified 3 GW energy portfolio, and deploys Bitcoin mining and HPC datacenters in the United States, Bhutan, Norway, Canada, Malaysia, and Ethiopia. Role Overview: We are seeking a talented Design Verification Engineer to join our IC development team and help ensure the functional correctness and robustness of complex digital designs. In this role, you will work closely with design and verification teams to develop comprehensive verification environments, execute test plans, and contribute to high-quality silicon through systematic and coverage-driven verification. Job Summary: Apply UVM (Universal Verification Methodology), SystemVerilog, Verilog, and SVA (SystemVerilog Assertions) languages in verification tasks. Develop and implement state-of-the-art verification methodologies, including UVM, C/C++, co-simulation, system emulation, and mixed-mode simulation/emulation. Contribute to projects requiring advanced verification tools such as Palladium, HAPS, and Zebu platforms. Collaborate effectively within a team, ensuring high-quality deliverables. Key Responsibilities: Equipped with a strong understanding of the Design Under Test (DUT), including its architecture, interfaces, and functional requirements. Collaborate with verification and design engineers to define, review, and refine verification test plans based on design specifications. Implement test cases, stimulus, and test patterns to validate DUT functionality and corner cases. Execute simulations and analyze/debug RTL issues using waveform analysis and debugging tools. Run and maintain regression test suites to validate design changes and ensure design stability across development cycles. Monitor and improve functional and code coverage metrics, contributing to coverage-driven verification and verification closure. Document test cases, verification results, and coverage reports to support verification sign-off. Contribute to the development and maintenance of automation scripts, reusable verification components, and Verification IP (VIP) to enhance team productivity. Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or currently pursuing the degree for entry-level roles). Solid understanding of digital logic design and RTL development using Verilog or other Hardware Description Languages (HDL). Proficiency with AMBA bus protocols (AXI, AHB, APB). Hands-on experience with RTL simulation, debugging, and waveform analysis using industry-standard EDA tools (e.g., Synopsys, Cadence, or Siemens EDA / Mentor). Proficiency with SystemVerilog and modern verification methodologies such as UVM. Familiarity with Linux/Unix environments and scripting for automation (e.g., Bash, C Shell, Perl, or Python). Experience using version control systems such as Git or SVN in a collaborative development environment. Good analytical and debugging skills, with the ability to identify and resolve RTL and functional issues. Strong communication skills in English, both written and verbal, with the ability to document verification results clearly. Self-motivated, detail-oriented, and able to work effectively both independently and within a team environment. Preferred Qualifications Experience with one or more of these technologies: NoC (network on chip), PCIe (Gen-4 onwards), DRAM memory controller. Experience with using AI Agent for verification productivity. Familiarity with RISC-V processor architecture or CPU verification concepts. Experience with C/C++ programming for testbench development or verification utilities. Exposure to coverage-driven verification and regression automation workflows. What you will experience working with us: A culture that values authenticity and diversity of thoughts and backgrounds; An inclusive and respectable environment with open workspaces and exciting start-up spirit; Fast-growing company with the chance to network with industrial pioneers and enthusiasts; Ability to contribute directly and make an impact on the future of the digital asset industry; Involvement in new projects, developing processes/systems; Personal accountability, autonomy, fast growth, and learning opportunities; Attractive welfare benefits and developmental opportunities such as training and mentoring. -------------------------------------------------------------------- Bitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. Bitdeer does not discriminate against employees or applicants based on conditions such as race, colour, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.