Senior Staff Physical Design Engineer – Contractor/Freelance (FinFET Specialist)
verticalcompute
Grenoble, Auvergne-Rhône-Alpes, France · Grenoble · France
Posted Mar 16, 2026
- Full-time
- Hybrid
- Design
- experienced
verticalcompute
Grenoble, Auvergne-Rhône-Alpes, France · Grenoble · France
Posted Mar 16, 2026
About Us
Vertical Compute is an early-stage deep tech startup dedicated to pioneering next-generation memory technologies for advanced computing architecture. Our mission is to redefine the well-known trade-offs of semiconductor memory devices, ultimately enabling the future of computing.
We are welcoming passionate, experienced, and forward-thinking colleagues to join our dynamic team and disrupt the industry together.
About What You Will Do
As a Senior Staff Physical Design Engineer, you will take technical leadership in the physical implementation of next-generation high-performance SoCs targeting 16nm FinFET technologies and below.
In this role, you will:
Lead the full RTL-to-GDSII physical implementation flow, including synthesis, floorplanning, place & route, CTS, timing closure, and sign-off.
Define and execute implementation strategies optimized for FinFET technologies, addressing challenges such as secondary power grids, track patterns, and advanced DRC constraints.
Perform Multi-Mode Multi-Corner (MMMC) timing closure and power optimization to achieve the best PPA (Power, Performance, Area) targets.
Conduct power integrity analysis and ensure robust IR drop and electromigration (EM) margins.
Drive physical verification closure including DRC, LVS, ERC, and antenna checks using industry-standard sign-off tools.
Collaborate closely with RTL and DFT teams to ensure physically aware synthesis, efficient scan-chain integration, and congestion mitigation.
Interface with foundries and EDA vendors to address technology-specific implementation challenges.
Contribute to EDA flow improvements and automation through scripting (Tcl, Python, or Perl) to enhance productivity and design quality.
Act as a technical pillar and mentor within the physical design team, supporting complex debugging and advanced optimization strategies.
About who you are:
Master’s in Electrical Engineering or related field.
10+ years in full-custom layout for memory and/or analog/mixed-signal IPs.
Deep understanding of physical constraints: matching, EM, IR drop, antenna rules.
Proficient in layout tools (Virtuoso, Calibre), proficiency in CAD scripting is considered as a big plus.
Experience with advanced CMOS nodes and emerging memories (MRAM, RRAM) is a plus.
Experience in in-memory computing layout is a plus.
Self-motivated, self-directed, and well-organized.
We like to build a high performing dream team and count on your excellent communication and interpersonal skills, and ability to engage effectively with your colleagues, our partners, and stakeholders.
Good English communication skills, knowledge of French and/or Dutch is considered a bonus.
Why Join Us:
You will get the opportunity to work at the forefront of memory technology innovation.
Vertical Compute is not only a state-of-the art but also a human adventure. We believe you must have a lot of fun developing the best of you. Making sure you and your team are going to enjoy the journey and become passionate about what we do is a key goal of our founders.
You can be part of a talented and dedicated team in a fast-paced startup environment.
In this role, you contribute to projects that will have a significant impact on the future of computing and electronics.
You can count on a motivating total rewards package.
How to show your interest in our vacancy: Does the above sounds like you are ready to join our team, please upload your CV.
Vertical Compute is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Join us in shaping the future of compute & memory technology and celebrating success!