SI Simulation Engineer

Job description

**About Ubiquiti** At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities - Perform pre-layout and post-layout signal integrity simulation for high-speed interfaces, including DDR4/DDR5, PCIe Gen3–Gen5, and 100G/400G/800G Ethernet. - Evaluate channel loss, PCB material, stack-up, IC placement, and routing constraints during the early design stage. - Build and analyze end-to-end channel models, including PCB traces, vias, connectors, cables, packages, and IC models. - Optimize high-speed channel structures, including vias, anti-pads, connector launches, cables, and routing topology. - Analyze insertion loss, return loss, crosstalk, impedance discontinuity, jitter, eye diagram, and BER performance. - Define PCB layout guidelines and routing constraints for high-speed interfaces. - Work with EE, layout, mechanical, vendor, and validation teams to review designs and resolve SI issues. - Support simulation-to-measurement correlation using VNA, TDR, oscilloscope, BERT, or compliance test results. Qualifications - Bachelor’s degree or above in Electrical Engineering, Electronics Engineering, or a related field. - 5+ years of experience in high-speed signal integrity simulation and PCB channel design. - Hands-on experience with Ansys simulation tools, such as HFSS, SIwave, Q3D, or AEDT. - Familiar with high-speed interfaces, including: - DDR4,DDR5 - PCIe up to Gen5 - IEEE 802.3by / 802.3bm / 802.3bs / 802.3cd,100G / 400G / 800G Ethernet - Strong understanding of high-speed channel behavior, including insertion loss, return loss, crosstalk, impedance discontinuity, jitter, eye diagram, and BER. - Ability to define practical PCB routing constraints and provide design recommendations. Preferred Qualifications - Experience with 25G / 56G / 112G SerDes channel design. - Experience with switch, router, server, NIC, AI server, or high-speed backplane products. - Knowledge of low-loss PCB materials, Dk/Df, copper roughness, and glass weave effects. - Familiar with IBIS-AMI models, S-parameters, equalization tuning, and channel operating margin analysis. - Experience creating SI simulation reports, layout guidelines, and design checklists. - Experience supporting lab validation and debugging SI-related issues.