Sr Staff/ Staff Engineer: Physical Design

**About us:** Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. Mythic's unique technology makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised over USD 125M in a recent funding round and has offices in Palo Alto (CA, USA), Austin (TX, USA), and Bangalore (Karnataka, India). **About This Role:** Mythic is a fast-paced AI startup seeking passionate engineers who thrive in dynamic environments and embrace broad, flexible roles. We are looking for hands-on Physical Design Engineers eager to push boundaries in advanced technology nodes. This role is for Mythic’s Bangalore design center, but as part of our global workforce across geographies, you will drive innovation by working closely with the RTL and Technology teams and contribute to producing high-quality designs through first-pass silicon success. With end-to-end ownership, you’ll tackle challenges in physical design with a focus on scalability, speed of execution, and efficiency in a fast-moving AI hardware landscape, with a strong emphasis on analog IP integration. This role is for experienced, seasoned engineers who are well-versed in PD flows, with a proven record of execution, and who are driven to push the envelope and find innovative solutions to complex implementation challenges at both the subsystem and chip levels. ### Here is what you will do: - Participate in the development of **Physical Design (PD) methodologies** across the RTL-to-GDSII flow using industry-standard tools (Cadence, Synopsys, Mentor). - Perform lead level hands-on work in one or more areas including **Synthesis, Formal Equivalence, Place & Route (PnR), Static Timing Analysis (STA), DRC/LVS/IR/EM Signoff** at both module and top level. - Take full **ownership of the physical design process** at the module level and provide support in top-level integration, collaborating closely with RTL designers, DFT teams, and fabrication partners. - Provide **technical mentorship**, guiding team members and managing PD team interactions to ensure successful SoC implementation. - Drive **PPA optimization**, including low-power clock tree design for high-performance systems, and achieve timing closure across multiple corners and use cases. - Champion an **automation-first approach**, developing methodologies in TCL, PERL, or Python to significantly improve team efficiency. ### Here is the background we hope you have: - [](http://B.Tech/M.Tech/PhD) in Electrical Engineering (**EE**) or Electronics & Communication Engineering (**ECE**). - **10+ years of experience** in the Physical Design domain. - Deep expertise in one or more areas (Synthesis, Formal Equivalence, PnR, STA, DRC/LVS/IR/EM signoff) with strong working knowledge of the entire PD flow. - Proven track record of successful tapeouts for **multi-million gate, multi-hierarchy designs** at advanced nanometer technology nodes. - Solid understanding and preferably hands-on experience in **low-power design and implementation strategies**. - Strong background in **automation of PD methodologies** using TCL, PERL, or Python. - Willingness to expand beyond core expertise, with a **team-oriented, can-do attitude** and commitment to mastering the full RTL-to-GDSII flow. ### The following would be nice to have, but is not required: - Knowledge of **chiplet-based design limitations** and their impact on physical design. - Experience in Sub-10nm designs - Familiarity and hands-on experience with **Cadence toolsets**.