Staff ASIC Design Engineer

Job description

Company Description Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world’s most critical infrastructure—from data centers to next generation cloud and AI platforms—by securing systems at the foundation levels of hardware, independent of host CPUs and operating systems. Founded in 2019 and now over 150 employees are strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders, validating both our technology and our long-term market trajectory. Axiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Company’s 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award. At Axiado, developing breakthrough technology takes more than great engineering—it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world. If you’re driven to innovate, energized by hard problems, and excited to help define the future of secure AI infrastructure, we invite you to apply and join us on this journey. Job Description We are seeking a talented and innovative Staff ASIC Design Engineer to join our dynamic team in Hyderabad, India. In this role, you will take ownership of critical ASIC design projects, driving the development and implementation of sophisticated System-on-Chip (SoC) solutions. You will collaborate with cross-functional teams to deliver high-quality silicon products from concept through production maturity. This is an excellent opportunity for an experienced design professional to make a significant impact on cutting-edge semiconductor technology while fostering innovation and technical excellence. Design and implement RTL blocks with a focus on micro-architecture optimization, ensuring efficient and implementable solutions Develop clear, comprehensive micro-architecture specifications and technical documentation for various design components Execute synthesis, timing closure, and optimization activities to meet performance and power requirements Collaborate effectively with firmware, software, design verification, FPGA, DFT, and backend teams throughout all stages of ASIC development Support prototyping activities, test program development, and comprehensive chip validation from initial bring-up through production maturity Conduct design bring-up and debug on FPGA-based emulation platforms, identifying and resolving complex technical issues Implement and analyze assertions and coverage metrics to ensure design quality and completeness Work with industry-standard interface protocols including PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, and SPI Mentor junior engineers and provide technical guidance on design best practices and methodologies Utilize scripting languages and repository management tools to streamline design workflows and maintain code quality Qualifications 7+ years of hands-on experience in RTL logic design, verification, synthesis, and timing optimization Demonstrated expertise in writing efficient, synthesizable RTL code in Verilog with strong SoC integration knowledge Proficiency in micro-architecture design and the ability to translate specifications into robust implementations Solid understanding of assertions, coverage analysis, RTL synthesis methodologies, and timing closure techniques Extensive experience with interface protocols such as PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, and SPI Proven experience with FPGA-based emulation platforms (HAPS, Veloce) for design validation and debugging Fluency with scripting languages including Perl and Python for design automation and tool development Experience with repository management tools (Bitbucket, Jenkins) and bug tracking systems (JIRA) Successful completion of at least one full tape-out cycle from design through silicon validation Strong communication and documentation skills with the ability to articulate complex technical concepts clearly Demonstrated ability to work collaboratively in cross-functional team environments Excellent analytical and problem-solving capabilities with attention to detail Preferred: Silicon bring-up and debug experience on actual hardware Preferred: Experience mentoring or leading junior design engineers Preferred: Familiarity with design methodologies, standards, and industry best practices Additional Information Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent. We are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence and high curiosity over pedigree alone. Working hard and smart, continuous learning and mutual support are all part of who we are. Axiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.