Staff Physical Design Engineer - SoC EMIR Engineer

asteralabs

Tel Aviv-Yafo, Tel Aviv District, Israel · Tel Aviv-Yafo · Israel

Posted Jun 7, 2026

Other
ASIC Engineering

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments.

Key Responsibilities

Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip
Collaborate closely with Physical Design team to insure a full power integrity
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)
Understand root-cause analysis for voltage drop violations and EM risks

Basic Qualifications

Bachelor's or Master's degree in Electrical Engineering or a related technical field
7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)
Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)
Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM

Preferred Experience

Familiarity with thermal analysis tools and their interaction with electrical performance
Experience working with sign-off criteria and margins for high-volume production chips
Good understanding of timing and P&R
Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution
Ability to write TCL scripts for STA and Fusion Compiler (FC)

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.